The work plan follows the path from theoretical developments and algorithms at the signal modeling level to the definition of architectural components optimized for compressive sensing and ultra-low power operations, their integration within heterogeneous 3D architectures and the mapping of system level primitives seeking to deploy effective power management policies for the target architecture. To enforce the holistic approach we advocate in PHIDIAS, there is a very clear streamline between workpackages.
The first workpackage will produce and validate the sparse signal models that are necessary to apply compressive sensing (WP1, led by EPFL). Based on these models, sensing strategies will be derived with a strong emphasis on selecting those that are amenable to low-power architectures.
WP2 will focus on developing architecture components, both analog and digital, that are suited for the CS-based sensing strategies selected in WP1, in particular the ultra-low power analog front-end. Partners involved in WP2 will coherently design and deploy circuit-level architecture allowing to perform all CS computations at ultra-low power.
WP3 will go one step further, performing hardware/software co-design. Partners in WP3 will help analyzing requirements of the identified application and architecture components and will specify the overall architecture from both a hardware and software viewpoint.
Finally WP4 will ensure the global validity and coherence of the whole approach by exploring the methods to achieve an effective mapping of the CS-based system-level signal processing analysis, as well as deploying effective power management approaches for the target architecture. Both thrusts will ensure that the optimizations performed in WP2 and WP3 are perfectly integrated.